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  • It Job for B.TECH Graduates  at Cadence Design Systems in noida,mumbai,delhi,kolkata,chennai,bangalore,hyderabad | JobLana Powered by Blockchain | Joblana
    It Job for B.TECH Graduates  at Cadence Design Systems in noida,mumbai,delhi,kolkata,chennai,bangalore,hyderabad | JobLana Powered by Blockchain | Joblana
    Cadence Design Systems



    IT
    About the Company

    Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that after an extensive competitive evaluation, Cypress Semiconductor Corp. selected the full Cadence® RTL-to-signoff digital design flow and complete Spectre® circuit simulation platform for all of its 40nm automotive chip designs. The evaluation process showed Cypress the opportunity to dramatically improve its turnaround time and productivity with the Cadence solution when compared with its previous flow. The Cadence digital flow consists of the Innovus™ Implementation System, the Genus™ Synthesis Solution, the Tempus™ Timing Signoff Solution, Conformal® Low Power and the Quantus™ QRC Extraction Solution. These tools collectively enabled Cypress to achieve improved individual tool throughput and productivity gains. Specifically, the Innovus Implementation System provided Cypress with significant power, performance and area (PPA) benefits.


    Job Profile:
    22   Vaccancies for it in IT   at a CTC of    INR   4 - 5 L.P.A.

    About Job

    At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The candidate will responsible for contribution in development of Digital Mixed Signal Interoperability Solution between various tools within Cadence. Candidate should have understanding of Mixed Signal Design challenges and Cadence Chip Designing tools like Virtuoso & Encounter. He/She will be responsible for designing and developing the interoperability solution in C/C++ on Linux/Sun/Solaris platform.

    Locations of work

    Noida
    Mumbai
    Delhi
    Kolkata
    Chennai
    Bangalore
    Hyderabad

    Eligiblity Criteria
    Min-Education : Graduation
    Min-Qualification : Bachelor of Technology (B.Tech)
    Experience : 36 Month


    Requirements
    1. BS - CS/CE/EE with EDA experience and C++ development OR.
    2. MS - CS/CE/EE with 3+ years EDA experience and C++ development preferred.
    3. Understanding of the Mixed Signal Designs.
    4. Good development experience in C/C++, data structures and algorithms.
    5. Working knowledge of TCL and Skill
    6. Software development processes - writing spec’s; doing code reviews; testing; purecov/gcov/valgrind/collector, etc.
    7. Experience in developing large-scale software.
    8. Self-motivated with very sharp analytical skills.
    9. Good understanding of Cadence Design Tools like Virtuoso and Innovus.